Tape-in May 2024

Pinout

Verilog Pin	Function
io 5	output adapter_parity
io 6	output minion_parity
io 7	input minion CS
io 8	input minion MOSI
io 9	input minion sclk
io 10	output minion MISO
io 11	input xbar input override
io 12	input xbar output override
io 13	classifier xbar input override
io 14	classifier xbar output override
io 15	output xbar input override
io 16	output xbar output override

Messages are 20 bits wide, with 4 bits being address bits and 16 bits being data bits. Address mapping is as follows:

Address	Input Behavior	Output Behavior
0	Input XBar SPI inject	Input XBar SPI out
1	Input XBar config	N/A
2	Classifier XBar Inject	Classifier XBar out
3	Classifier XBar config	N/A
4	Output XBar inject	Output XBar SPI out
5	Output XBar config	N/A
6	Classifier set cutoff frequency	N/A
7	Classifier set cutoff magnitude	N/A
8	Classifier set sampling frequency	N/A