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ProjectResponsible Engineer
Wishbone


Classifier
FFT Re-Write
Testing Previous Tapeout
Integration
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  1. user-57cad Mika Finkman Edmund Lam Steven Sun Tomas Ian Choi Johnny Julian Martinez Vicky Minh Le user-f6da1 Christopher David Schiff Kevin Liu Fantastic demos today! Even though I couldn't be there (sad), it was great to see what everyone had accomplished. The main action items I saw from the demos were:

    • More tests in general, if possible (smile)
    • Investigate possible bug with AND reduction in Verilator?
    • Great job following coding guidelines! Helps out a lot when others read your code (smile)
    • Possibly testing within the DSLX framework instead of Python?
    • Making sure we have final tapeout (Tapein 2.5) tested on the FPGA
    • Possibly flush out val/rdy protocol for Wishbone?

    Overall, REALLY impressive job, not only with the technical aspects, but being able to coordinate with the entire team. Super excited to see the final result!!