https://github.com/cornellcustomsiliconsystems/C2S2-Module-Library/tree/valrdyqueue
We want to create a Valid-Ready interface that we can use any time we have 2 blocks that need to communicate with each other. The block diagram is shown below:
There are several implementations of the shift register. Currently, options are as follows:
- a serial-in-serial-out shift register, with load
- a serial-in-parallel-out shift register, with load
- a parallel-in-parallel-out shift register (WIP)
Interface
The interface of the val-rdy block can change depending on how we want to send the data. The val and rdy signals are always 1 bit wide, but the width of data_in and data_out can vary. If we are using a serial-in-serial-out shift register, both would be a single bit wide. If we are using serial-in-parallel-out, data_in would be 1 bit wide and we would set data_out to be however wide we want our packets to be. If we are using parallel-in-parallel-out, data_in and data_out should be the same width.
The sender and receiver handle the setting of val and rdy internally, so that all our block has to do is handle the logic concerning when we should send data. It is pretty simple (only send data when the data is valid and the receiver is ready to receive it).
Testing
To test the module, I first tested the shift registers. Once it was clear that those worked as expected, I moved on to testing the val-rdy block as a whole. There was not a lot of functionality added on top of the shift register, so testing was rather straightforward. For all modules tested, the overall strategy was to try some standard test cases, and then try to cover as many edge cases as possible.
Evaluation
TBD, still need to push through flow. Plan on making some graphs that show area, energy as a function of bit width/queue size.