Questions:

  1. What considerations should we have regarding a minimum sample rate due to leakage in the MIM caps?
    1. Leakage should not be a big problem
  2. How to generate a Vcm for the comparators
    1. It is a big consideration to generate Vcm
      1. Take Vcm to a package pin 
    2. Consider using split capacitor
    3. Change comparator to accept Vcm 
    4. Use a "oh no bit" to choose a different Vcm
  3. What sort of considerations should we look into for the comparators? We were thinking auto zero triple tail
    1. Autozeroing could go wrong.. consider oh no bit
    2. Could increase accuracy by 1lsb
    3. Be very considerate of auto-zero capacitor, could be troublesome from mismatch
    4. buffer the clock!
      1. the clock buffer here may be easiier to implement without standard cell
  1. Are there any recommendations for sampling technique? For now we have conventional bottom plate sampling that is differential.
  2. Do we scale down our analog switch width in accordance with the capacitor size within the array?
  3. How much of a problem is kickback? How do we tell if our kickback is acceptable or not? 
    1. it will exist, and simulate it
    2. Kickback could could confuse comparison
    3. If kickback causes a diode to get forward biased, voltage will be lost. This is very bad. (small kickback should be ok?)
    4. Kickback could from parasitic gate drain capacitor. 
    5. Check your cascode
    6. Maybe have that node not clocked
  4. How do you recommend we do layout for the CDAC? It seems like that would take a lot of time.
    • CDAC is very challenging → hand layout is typical
      • 8 bit should be quite easy
      • Create a pattern
    • Routing is a problem – ensure no crosstalk
    • Put a big sheet of metal on M5
    • Put a big sheet of metal on M2 and pop in vias. 
    • Protect your capacitors!
    • This introduces parasitics, but these are static
    • Consider aggressors and victims (what nodes)


  • Have a separate AVDD and AVSS could be useful
  • Make sure that things that cross between digital and analog boundaries are cleaned up
  • Make sure Ir drop across vdd is not too much
  • Vref+ and - being cnnected to the CDAC is OK. 
  • Boostrapped switch is ok, but may not be necessary. Also be careful of bootstrapped extra voltages. 
    • Bootstrapped switch is good for Ron linearity
    • not particularrly necessary
    • Have to be a bit careful about substrate to source/gate
    • gate to body should not be a big deal
    • Vgs and Vds are a big deal 
    • Think about startup and turnoff behavior
  • Grab some extra bits for trim bits from digital for risk mitigation
  • Think about testing/safety
  • Calibrating charge injection away is a possibility
  • Can protect the body of the transistor for the deepnwell
  • Break before make
    • Look for some standard cells that provide delay (dly cell?)
    • Concentrate as much digital as possible in as few blocks as possible in layout
    • P and notP should be driven by 8x inverters
  • FSM logic
    • Should not be too bad
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