Page History

A piece of hardware meant to accelerate a specific task. This is useful when you know that you are likely to be performing a specific task over and over again, and wish to have dedicated hardware to perform it. For example, if you are designing a chip to go in a car, you might have an A* algorithm accelerator to speed up the computation of calculating the shortest route to a destination.

Many designs also have accelerators coupled with general-purpose hardware. This allows for general computations, but adding the option to use the accelerator when beneficial.

A piece of hardware that converts an analog signal (with a continuous spectrum of values) to a digital signal (with discrete values). It is one of the projects for the Analog subteam '23-'24

A design principle that includes considerations of how the design might be tested, extending the design to make the testing process easier. This could include extra functionality and/or more exposure of the design (bringing more nets out to pins) to provide the tester with greater capability to test different parts of the chip.

(Note that this can also stand for Discrete Fourier Transform, which isn't as relevant to overall chip design)

A style of dynamic logic. Here, nodes are precharged high. Once indicated by a clock signal, the nodes are then evaluated; if required by the logic, they are pulled low. In doing so, we only need to implement the PDN, resulting in faster overall logic; domino logic is considered to be the fastest overall logic family, and is often used for high-speed arithmetic. However, it does come with some prerequisites:

• The inputs must be monotonically increasing, or else the dynamic node might be intermediately discharged when we want it to remain high. However, the outputs of the domino stage are monotonically decreasing, making them difficult to chain together. This can usually be resolved with intermediate inverters between stages, or with p-logic stages between the n-logic stages (introducing no-race, or NoRa logic)
• The inputs must be low before the evaluate stage, to avoid early discharging. If this cannot be guaranteed, a footer is used to prevent discharge in the precharge phase (which comes at the cost of higher capacitance that the clock must drive, as well as larger nMOS to maintain a balanced gate)

The process of introducing charge carriers into a silicon lattice. Silicon is a Group 4 element, and forms a nice lattice structure, with each Si forming 4 bonds with its neighbors. When we introduce Group 5 or 3 elements, these will abide by the lattice structure to produce 4 bounds, but will additionally contribute either an electron, or a lack of an electron (known as a hole), both of which can carry charge across the silicon. Because of this, doping comes in two types:

• p-type doping: Introducing Group 3 elements to generate holes in the silicon (usually Boron or Gallium). This forms p-type silicon
• n-type doping: Introducing Group 5 elements to generate electrons in the silicon (usually Arsenic or Phosphorus). This forms n-type silicon

A step in the ASIC flow that determines the final placement of cells. This is after global placement has approximately placed all cells; with detailed placement, we're resolving any overlapping cells, as well as ensuring correct abutment contacts (such as for power and ground rails). This ability to limit our scope makes the final placement process easier.

A type of RAM that passively holds the state (dynamically). It is composed of an access transistor and a capacitor. When we want to access the cell (either to read or write), we set the access transistor to allow current flow, and either charge/discharge the capacitor (write) or read the stored value (read). Given that capacitors naturally discharge over time, DRAM cells must be periodically refreshed. However, capacitors can be made to have a small footprint (look up trench capacitors). Because of this, when compared to registers and SRAM, DRAM uses the least area for a given amount of memory (is the most dense). It additionally uses the least power, at the cost of being the slowest to access.

The process of checking whether our design is manufacturable, according to our PDK. This includes checking the dimensions of transistors, whether traces are too close or far, as well as if we have any antenna violations. This does not check whether our design functions as intended - that is done by LVS, leading to the two often being performed together. If a design has no DRC errors, it is said to be DRC clean.

If your design is not DRC clean, not only will it not be manufactured correctly, but it may cause damage to the fabrication machines. Because of this, a foundry will not manufacture any designs that are not DRC clean.

A step in the ASIC flow that determines the final routing of cells. This comes after global routing, which routes all long global wires to their approximate destinations. With detailed routing, we take a local view of any remaining routing, and ensure that our traces connect to all of our cells. This ability to limit our scope makes the final routing process easier.

A testing methodology that isolates a design as the "design under test". Much of the surrounding framework is abstracted to functional-level models, to isolate the exact component we're testing. Specifically, DUT frameworks often include:

• Generator: Generates the inputs for the DUT
• Driver: Delivers the generated inputs to the DUT
• Monitor: Monitors the output ports (and occasionally input as well) to capture the results of the inputs
• Scoreboard: Compares the outputs of the DUT with the expected outputs
• Environment: Contains the Generator, Driver, Monitor, and Scoreboard, for later re-use (possibly across different modules)
• Test: A given Environment with specific configurations. These configurations can later be tweaked for a different Environment configuration

A style of logic or memory where information is stored dynamically; it is held only temporarily. An example is DRAM, where our memory is held by a large capacitor, but is only held temporarily (leading to the need for a periodic refresh of DRAM memory)

A type of power consumption that occurs from the switching of transistors and computation. Current is used to charge the gate of transistors, and is dumped to ground when they are discharged, leading to power consumption. This is the opposite of static power consumption.

A timing constraint present in synchronous circuits. Specifically, hold time is the amount of time that an input signal (to a register) must remain constant after a clock's positive edge. If the clock edge causes this input to change within our hold margin (the amount of time after an edge with a duration of our hold time), the output and stored state may be unpredictable; in this case, we have violated hold time.

Compared to setup time violations, this is far worse issue; hold time violations are near impossible to fix after tapeout. There are some tricks that can be played (such as cooling the chip or running at a lower voltage to increase signal propagation time), but to a large extent, they are "chip killers", and should be treated with diligence.

A separate or embedded language (relative to our normal HDL) that is meant purely for verification, as opposed to the simulation or synthesis that our HDL is meant for. HVL's often include (non-synthesizable) higher-level constructs and functionality to assist the user in testing their design, such as stimuli generators and assertions, many of which are often wrapped in an object-oriented presentation. Examples include OpenVera, PSL, and the SystemVerilog Verification Subset.

(Note: On Project Teams specifically, HVL can also refer to the High Voltage Laboratory, a (now non-functional) off-campus power maintenance building that is used by some teams for storage. If you hear a random person in the ELL reference HVL, they're probably not verifying a hardware design)