Acronyms and Vocabulary

The process of simulating an RTL design with each net capable of being in 2 possible states:

• 0: Driven to the low voltage of the design (a digital "0")
• 1: Driven to the high voltage of the design (a digital "1")

Because of this, the representation of the design is very limited, and 2-State simulators often make some assumptions (such as uninitialized nets being a logical 0). This means that simulating a design using a 2-State RTL simulator, while fast and useful for early debugging, isn't sufficient; we should aim to verify our designs additionally under 4-State and GL simulations.

The process of simulating an RTL design with each net capable of being in 4 possible states:

• 0: Driven to the low voltage of the design (a digital "0")
• 1: Driven to the high voltage of the design (a digital "1")
• X: Ambiguous (uncertain as to which state it is driven to). This occurs on start-up before reset, as well as if registers capturing inputs are undefined
• Z: (High impedance) Not driven

This is an improvement over 2-state simulation, which only accounts for 1's and 0's. Many 2-state simulators will implicitly assume that nets initially begin at 0, and that non-driven nets are 0 as well. By using 4-state simulation, we can aim to catch some of these errors. It is not as encompassing as GL simulations, but is significantly faster.

A piece of hardware meant to accelerate a specific task. This is useful when you know that you are likely to be performing a specific task over and over again, and wish to have dedicated hardware to perform it. For example, if you are designing a chip to go in a car, you might have an A* algorithm accelerator to speed up the computation of calculating the shortest route to a destination.

Many designs also have accelerators coupled with general-purpose hardware. This allows for general computations, but adding the option to use the accelerator when beneficial.

A piece of hardware that converts an analog signal (with a continuous spectrum of values) to a digital signal (with discrete values). It is one of the projects for the Analog subteam '23-'24

An effect where a voltage difference on the body of a transistor (relative to the source) can change the threshold voltage of the transistor. 

• If an nMOS body is connected to a lower voltage than the source, the body will push electrons away, meaning that the gate needs to do more work to bring them back and invert the channel, resulting in a higher threshold voltage (V_th)
• If an pMOS body is connected to a higher voltage than the source, the body will attract, meaning that the gate needs to do more work to push them away to create holes and invert the channel, resulting in a higher threshold voltage (V_th)

The reverse is also true (a higher voltage nMOS body/lower voltage pMOS body will lower the threshold voltage)

A design principle that includes considerations of how the design might be tested, extending the design to make the testing process easier. This could include extra functionality and/or more exposure of the design (bringing more nets out to pins) to provide the tester with greater capability to test different parts of the chip.

(Note that this can also stand for Discrete Fourier Transform, which isn't as relevant to overall chip design)

A style of dynamic logic. Here, nodes are precharged high. Once indicated by a clock signal, the nodes are then evaluated; if required by the logic, they are pulled low. In doing so, we only need to implement the PDN, resulting in faster overall logic; domino logic is considered to be the fastest overall logic family, and is often used for high-speed arithmetic. However, it does come with some prerequisites:

• The inputs must be monotonically increasing, or else the dynamic node might be intermediately discharged when we want it to remain high. However, the outputs of the domino stage are monotonically decreasing, making them difficult to chain together. This can usually be resolved with intermediate inverters between stages, or with p-logic stages between the n-logic stages (introducing no-race, or NoRa logic)
• The inputs must be low before the evaluate stage, to avoid early discharging. If this cannot be guaranteed, a footer is used to prevent discharge in the precharge phase (which comes at the cost of higher capacitance that the clock must drive, as well as larger nMOS to maintain a balanced gate)

The process of introducing charge carriers into a silicon lattice. Silicon is a Group 4 element, and forms a nice lattice structure, with each Si forming 4 bonds with its neighbors. When we introduce Group 5 or 3 elements, these will abide by the lattice structure to produce 4 bounds, but will additionally contribute either an electron, or a lack of an electron (known as a hole), both of which can carry charge across the silicon. Because of this, doping comes in two types:

• p-type doping: Introducing Group 3 elements to generate holes in the silicon (usually Boron or Gallium). This forms p-type silicon
• n-type doping: Introducing Group 5 elements to generate electrons in the silicon (usually Arsenic or Phosphorus). This forms n-type silicon

A step in the ASIC flow that determines the final placement of cells. This is after global placement has approximately placed all cells; with detailed placement, we're resolving any overlapping cells, as well as ensuring correct abutment contacts (such as for power and ground rails). This ability to limit our scope makes the final placement process easier.

A type of RAM that passively holds the state (dynamically). It is composed of an access transistor and a capacitor. When we want to access the cell (either to read or write), we set the access transistor to allow current flow, and either charge/discharge the capacitor (write) or read the stored value (read). Given that capacitors naturally discharge over time, DRAM cells must be periodically refreshed. However, capacitors can be made to have a small footprint (look up trench capacitors). Because of this, when compared to registers and SRAM, DRAM uses the least area for a given amount of memory (is the most dense). It additionally uses the least power, at the cost of being the slowest to access.

The process of checking whether our design is manufacturable, according to our PDK. This includes checking the dimensions of transistors, whether traces are too close or far, as well as if we have any antenna violations. This does not check whether our design functions as intended - that is done by LVS, leading to the two often being performed together. If a design has no DRC errors, it is said to be DRC clean.

If your design is not DRC clean, not only will it not be manufactured correctly, but it may cause damage to the fabrication machines. Because of this, a foundry will not manufacture any designs that are not DRC clean.

A step in the ASIC flow that determines the final routing of cells. This comes after global routing, which routes all long global wires to their approximate destinations. With detailed routing, we take a local view of any remaining routing, and ensure that our traces connect to all of our cells. This ability to limit our scope makes the final routing process easier.

A testing methodology that isolates a design as the "design under test". Much of the surrounding framework is abstracted to functional-level models, to isolate the exact component we're testing. Specifically, DUT frameworks often include:

• Generator: Generates the inputs for the DUT
• Driver: Delivers the generated inputs to the DUT
• Monitor: Monitors the output ports (and occasionally input as well) to capture the results of the inputs
• Scoreboard: Compares the outputs of the DUT with the expected outputs
• Environment: Contains the Generator, Driver, Monitor, and Scoreboard, for later re-use (possibly across different modules)
• Test: A given Environment with specific configurations. These configurations can later be tweaked for a different Environment configuration

A style of logic or memory where information is stored dynamically; it is held only temporarily. An example is DRAM, where our memory is held by a large capacitor, but is only held temporarily (leading to the need for a periodic refresh of DRAM memory)

A type of power consumption that occurs from the switching of transistors and computation. Current is used to charge the gate of transistors, and is dumped to ground when they are discharged, leading to power consumption. This is the opposite of static power consumption.

A type of photolithography that uses ultraviolet light with a very small wavelength (13.5nm or lower) when exposing the resist. Since our feature size scales with our wavelength (as our feature size depends on the amount of diffraction, which depends on the wavelength), this process allows for very small features. Previous processes were able to achieve a similar feature size through tricks such as OPC, lenses, and different phases; since EUV largely cannot use these techniques (due to most materials absorbing EUV radiation), the jump in overall feature size was less than anticipated by the time it occurred.

At time of writing, the only manufacturer of EUV systems is ASML, targeting 5nm and 3nm nodes. Due to the high quality of the machine and the many high-quality suppliers ASML must source from, an EUV system will currently cost you around $200 million.

See Foundry

A given gate's fanout is the amount of output capacitance it is driving relative to its input capacitance. For example, if an AND gate's output was an input to three other AND gates, it would have a fanout of 3. If it were to instead drive 5 inverters, each of which had half the input capacitance of the AND, it would have a fanout of 2.5.

The transition of a digital signal from a logical 1 to a logical 0. This transition of a clock signal is rarely used to transfer data compared to its rising edge (unless we're doing something silly like DDR - if you're curious, out of scope for here, but look it up )

A mathematical operation that takes a time domain signal and converts it into a frequency domain signal. Specifically, a Fast Fourier transform attempts to speed up the computation by eliminating many of the redundant operations originally present in the Fourier algorithm. This was the design present on C2S2's Digital Spring 2023 tapeout!

Metal shapes inserted on our chip that serve no logical purpose. Instead, their role is more structural, serving to keep our metal density/distribution even across the layer to avoid variations in thickness after CMP.

A standard cell that doesn't have a logical function, but is instead used to ensure power connections by abutment. Often times, our standard cells get their power and ground from their neighbors, relying on the fact that power and ground will be in the same location across all standard cells. During placement, we may find that our standard cells are spaced out, meaning that power and ground won't be connected. Our filler cells are just these connections, and are placed in the gaps to ensure that power and ground can go from one neighbor to another.

A style of transistor occurring in small process nodes (nominally 22nm or below). They have the area of diffusion sticking up perpendicular to the substrate, instead of laying parallel on top (looking up a picture helps). This allows the gate of the transistor to wrap around this area and cover three sides, giving the gate much more control over the source-drain current (lowering the threshold voltage, saving power...all sorts of good stuff). Future development include "gate all-around"; which this is mostly theoretical at time of writing (Intel claims they'll be able to do it ), it would have the gate wrap entirely around the diffusion area to allow for maximum control of the transistor current.

A method of connecting the interconnects of a die to other dies and its packaging (specifically, the leadframe). Specifically, flip chip calls for turning the die upside-down, such that the top layer of metal (now on the bottom) can directly contact the packaging to connect. Compared to wire bonding, the primary advantage is the density of interconnects (proportional to area, not just the perimeter), as well as shorter interconnects (leading to faster speeds). However, this comes at the cost of more complicated, less flexible manufacturing, as well as the cost to manufacture.

The process of (or result of) determining where our design will be placed on our silicon die, and how much area it will take up. Often times, there is non-negligible overhead in routing our design; because of this, our floorplan might not be as compact as it could be. However, it's difficult to know this overhead exactly beforehand, as we have to know where our design is located before routing. Because of this, our floorplan tool will often target a specific density of our design; how close together all of the blocks and standard cells should be. 

After routing, there may be leftover space because of this. This is often filled with other devices to ensure a quality CMP process; these may be non-functional, but a common choice is decoupling capacitors to ensure a smooth and steady voltage supply.

An "automated" process to turn an RTL design into a final GDS file. "Automated" is in quotes, as the tools involved usually need a fair amount of help and guidance from the user to generate a good design. While all flows are different, the common steps (in rough order) are:

1. Synthesis (and GL simulation)
2. Floorplanning
3. Placement
4. CTS
5. Diode Insertion (if applicable - see Antenna Violations)
6. Routing
7. DRC
8. LVS
9. Extraction (and Back-Annotated GL Simulation)

A 2-dimensional diagram of the connections of a component to the PCB. To include a component in your PCB design, you need its footprint in order to know the location and size of each connection.

The place/company/entity that fabricates the final design (the factory). Previously, this was often lumped in with the designers (leading to vertically integrated chip design). However, more modern trends have seen a separation of fabrication from design, and many design companies going fabless. This allows the designers and foundries to work with many more partners, but additionally poses challenges in maintaining the security of IP.

Some examples of foundries are TSMC, Skywater, and Global Foundries.

Some examples of fabless designers are Qualcomm, Broadcom, Nvidia, Xilinx, AMD, Marvell, and eFabless.

Some examples of integrated companies include Intel and Samsung.

A reconfigurable piece of hardware that can emulate hardware designs. It does this through many programmable lookup tables (LUTs) which are all interconnected, allowing the user to program the FPGA to emulate hardware by defining the output logic of the LUTs and how they are connected. Due to their programmability/flexibility, FPGA's aren't as efficient as ASIC designs. However, they are still much faster than simulations of hardware, with their flexibility causing many consumers to use them (ex. to train your neural network, instead of having to go through the tapeout process with a high startup cost to make an ASIC to do it, companies will rent you out time on their FPGA's, saving you money). In general, FPGA's are preferred for small quantities, whereas ASICs are preferred for large quantities (with the crossover point varying, but currently around 100,000)

A design that includes an internal piece of "state" (of which there are predefined options) that represents the current status of the design. When designing an FPGA, we need to consider the three following items:

1. States: What are the possible states for our machine? How will we represent the state?
2. Transitions: Under what conditions will we transition states? If I'm in State X, what determines my next state?
3. Outputs: Given our current state, what should our outputs be? In this manner, FSM's come in two flavors:

• • Moore Machine: The outputs only depend on our current state
  • Mealy Machine: The outputs depend both on our current state and our inputs

Gates included to intentionally restrict the flow of signals for power consideration. If we aren't using a portion of our design, we may gate signals to it in order to save power (as power spent on hardware doing nothing is wasted). This includes:

• Data Gating: Intentionally preventing the flow of data. If the data isn't changing/switching, our nets aren't being charged/discharged, saving dynamic power.
• Clock Gating: Intentionally preventing the propagation of a clock signal. This prevents our registers from taking new values, preventing the switching of nets and saving dynamic power
• Power Gating: Intentionally preventing power from being supplied. Since there is no voltage at all, this eliminates both dynamic and static power consumption. However, implementing power gating is difficult, as we have to have a logic gate that is also capable of efficiently supplying power when we want it.

A timing constraint present in synchronous circuits. Specifically, hold time is the amount of time that an input signal (to a register) must remain constant after a clock's positive edge. If the clock edge causes this input to change within our hold margin (the amount of time after an edge with a duration of our hold time), the output and stored state may be unpredictable; in this case, we have violated hold time.

Compared to setup time violations, this is far worse issue; hold time violations are near impossible to fix after tapeout. There are some tricks that can be played (such as cooling the chip or running at a lower voltage to increase signal propagation time), but to a large extent, they are "chip killers", and should be treated with diligence.

A separate or embedded language (relative to our normal HDL) that is meant purely for verification, as opposed to the simulation or synthesis that our HDL is meant for. HVL's often include (non-synthesizable) higher-level constructs and functionality to assist the user in testing their design, such as stimuli generators and assertions, many of which are often wrapped in an object-oriented presentation. Examples include OpenVera, PSL, and the SystemVerilog Verification Subset.

(Note: On Project Teams specifically, HVL can also refer to the High Voltage Laboratory, a (now non-functional) off-campus power maintenance building that is used by some teams for storage. If you hear a random person in the ELL reference HVL, they're probably not verifying a hardware design)

A hardware communication protocol intended for small distance communication, such as between chips or modules. It is a two-pin bus protocol using SDA (Serial Data) and SCL (Serial Clock), with data being transmitted on the clock edge. While the exact communication protocol (involving headers and ACK bits) is beyond the scope, one nice feature is that all lines are pulled high by default; to use, a transmitter will actively pull the lines low. This is how we can establish priority and avoid contention; if you as a transmitter are sending your header, and you notice that the line is pulled low when you want it to be high, some other transmitter is doing so, and you should relinquish priority to them. Compared to SPI (which occupies the same use space), while it requires fewer data lines as a bus protocol, it is not as fast (up to 400Kbps)

A collection of circuit elements integrated onto a single piece of silicon. While there is no consensus as to who first proposed/invented the IC, the first realization of an IC is generally given to Jack Kilby in 1958.

A product from an individual or group that is a result of their creativity, for which they have the rights to. While other industries have intellectual property, it is especially important in chip design; many companies license IP to build their designs, and additionally send their IP to foundries, where they need to be confident that it will be secure. Having designs fall into the wrong hands can be devastating for a company. As such, many companies have rigorous procedures to keep their IP secure, such as encryption, workflows, and general work practices. However, open-source designers don't need to worry about this, as their designs are meant to be publicly available, leading to increased collaboration and accessibility.

A specification that serves as a contract between hardware in software. In essence, the specification models a type of computer without defining the implementation. Included are the available instructions and semantics, data types, registers, any hardware support, and how I/O's are handled, to name a few. It informs hardware designers of what they are responsible for achieving in order to implement the ISA, as well as informing software designers of what functionality they have available. As long as both the software and hardware adhere to the ISA, they should be compatible. Examples include ARM, x86, RISCV, and many more.

Rules for sizing the layout of circuits. These circuits were designed in units of lambda, which was usually half of the minimum channel length. Other dimensions, such as the minimum spacing between traces or the required overhang for poly, were also defined in lambda. This way, one technology had progressed to a smaller size, all the designer would have to do to have their designs in the new technology is change their value for lambda, scaling down the entire design.

As processes developed, starting around 180nm, the intricacy of the rules and unequal scaling led to lambda rules being discarded in favor of measurements in raw microns. However, gaining an understanding of lambda rules gave physical designers a good idea and intuition behind what their designs could and "should" look like.

A phenomenon that occurs in CMOS technology. Due to the neighboring wells in the substrate, an nMOS and pMOS can form a PNPN regime, making them represent an unintentional cross-coupled BJT pair (or a thyristor, when referred to as one component). The danger of this is that the base currents for the BJT's can self-sustain one another, keeping them both perpetually ON and shorting V_DD to ground. The details of how it occurs is out-of-scope (feel free to research though!), but there needs to be some external interferance/excitation, as well as significant well/substrate tap resistance. Because of this, the wells and substrates often have multiple taps do decrease the resistance/drop on the connection, and packages are made out of radiation resistant material, to avoid excitations from alpha particles. Other solutions that can eliminate the possibility of latchup completely are silicon-on-insulator or shallow trench isolation techniques, as well as the more conventional triple-well CMOS approach.

(Fun fact: when IC's were being developed, many manufacturers noticed that they began to fail more in Denver for some reason. Later, we figured out that it was due to Denver's altitude and increased exposure to cosmic radiation, making the chip more vulnerable to latchup, as well as bit flips)

See M1/Metal1

A document of where "things" are located on a chip. This might be at a high-level with overall modules (i.e. a picture showing blocks in approximate locations to represent elements of the overall architecture), but can also refer to a more detailed specification, such as exact specifications of where metal is on the chip. The latter is generated by ASIC flows towards the end of the flow, but can also be created by hand through tools like Magic and Cadence Virtuoso.

Part of the packaging of an IC. Specifically, it is the metal frame that contains the leads. During the final step of manufacturing, the die is placed in the center, with connection to the leads occurring via either wire bonding or flip-chip. The entire frame is then surrounded by a black plastic (injection molding) before being separated, with the leads turning into the legs of the IC.

A static phenomenon where transistors that are "off" still let a little bit of current through (as they aren't perfect insulators). This "leakage current" can cause significant power consumption with no actual "work" done, and is therefore important to minimize. Leakage current decreases with increasing V_th

An abstracted physical view of the cell, including the PR boundary, pin position, and information about the layers involved. However, it does not contain the actual layout of the cell; that is contained in the DEF file, with both required for a complete view of a cell. They are denoted by the .lef file suffix

A file that specifies timing information about a cell. This includes the input and output capacitance of the cell, as well as the delay from every input to every output of the cell. Cells are often characterized by multiple LIB files for the many different corners. They are denoted by the .lib file suffix

The process of running your RTL design through a linting tool, a static analysis tool. Linting is used to assess whether your design will compile. In addition, it also aims to check for buggy or poorly-formed RTL, such as inferred latches, unused declarations, blocking vs. nonblocking assignments, unconnected ports, and multi-driven nets, to name a few. Many linting tools will check your RTL against thousands of guidelines and rules.

Linting can be a powerful tool, as it can help a designer catch errors in their design before running a simulation. This can be especially useful for very large designs, where running a simulation can take a very long time, but static checks will still be quick.

A planographic printing process. Chips specifically use photolithography, a method of patterning materials using light. If you hear someone in the semiconductor industry reference "lithography", they are referring to photolithography.

A table that takes in an input, and "looks up" a predefined output for that input. Commonly used in FPGA's to implement generic logic functions.

The process of confirming that our final design has the same functionality as our schematic. Our final layout is extracted, and compared against the layout; a design is said to be LVS clean if these two match, indicating that the layout will function the same as the schematic. However, this process gives no guarantees that the design can be manufactured - that is done by LVS, leading to the two often being performed together.

If a design isn't LVS clean, the IC will not function as you intend. However, it will still be manufacturable; because of such, a foundry does not care if your design is LVS clean (and will make your non-functional design regardless), so it is important you take the time to check it yourself.

A notation for the first metal layer. The many metal layers involved in routing the silicon on the chip are denoted by MX or MetalX, where X is the number of the layer, increasing "upwards"/away from silicon (think of them as floor numbers in a skyscraper, with silicon being the ground floor or basement). Often in chips, the layers will increase in pitch going upwards - as an example, M1 is very small and used only for local interconnects, but a layer like M9 will be much larger, and used for global signals that need to travel long distances with less resistance.

A representation of a block in your design. The block can be later substituted in, but in the meantime, is abstracted away to many different views. This allows for ease of processing; for example, when simulating the functionality of a block, we don't need the entire layout/GDS, but could instead use a functional representation, and switch the block in at a later point. A good example of this might be a custom memory block that we represent separately in Verilog.

Note that this is often what's done with standard cells in an ASIC flow; in this sense, standard cells are macros.

An open-source application that allows the user to manually create a layout by drawing the different layers of the chip. It also includes some integrated DRC and extraction tools.

A plate (usually made of quartz) that your designed is patterned onto. It only allows light to shine through in the pattern of your design, allowing for the pattern to be transferred in the photolithography process. The cost of making the masks for a wafer is the majority cost of manufacturing; this is why making one chip is very costly, but making 10,000 more is relatively trivial, allowing large companies to benefit from economies of scale.

The technology of creating microscopic devices that combine mechanical and electrical aspects. These are commonly incorporated onto chips when there is an innate need for a mechanical component due to the intended function, and can range from a few micrometers to millimeters. Their range of applicability is very extensive, including accelerometers, hard drive read/write heads, sensors, and beyond. 

A design principle that requires that different components of a design are able to be viewed separately, with well-defined interfaces. This not only allows for unit-testing of components in isolation, but for ease of replacement/extensibility; if you have a well-defined interface, you could connect a variety of components, so long as they support that interface as well.

Gordon Moore (1292-2023) was a co-founder of Intel. In 1965, while working at Fairchild Semiconductors, he was asked to contribute to the 35^th anniversary of Electronics magazine with a prediction of the semiconductor industry. He responded with a observation/prediction that the number of transistors on a chip will double about every 2 years (18-24 months, depending on who you ask). Despite it being a "wild extrapolation" (according to Moore), this observation held true well beyond Moore's expected lifetime of 10 years, and has been known as Moore's Law. The progress described by it has even been used as a target for the industry as a whole. In modern times, keeping with Moore's Law has become increasingly difficult; you may hear people talk about this being the end of Moore's Law.

A style of making capacitors with three layers; metal, oxide, and semiconductor. The metal and semiconductor serve as the ends of the semiconductor, with the oxide insulator as the dielectric. The capacitance (and the control the metal has over the channel in a MOSFET) can be increased with higher permittivity in the oxide (higher k), lower oxide thickness, or by modifying the work functions of the metal and semiconductor interfaces, such as with silicide between the layers.

The semiconductor is almost always made of silicon (although some research efforts have used germanium).

The metal used to be aluminum; however, this caused issues with more advanced processes, where the high temperature needed caused the aluminum to melt. Because of this, more modern nodes have used polysilicon (polycrystalline silicon) as a replacement. Even more recently, issues have been found when interfacing polysilicon with high-k dielectrics, leading for some processes (such as Intel 45nm) to return back to metal gates. It is still common to generally consider gates to be made of polysilicon.

The oxide was traditionally silicon dioxide (SiO₂). However, in an effort to get higher k and lesser tunneling current, other dielectrics have been used, such as hafnium dioxide (HfO₂). Silicon dioxide is often still included as a thin layer between the oxide and semiconductor to improve the work function and channel mobility.

A transistor where the source and drain are separated by a channel. Charge carriers can be pulled into this channel by the MOS capacitor (with the gate connected to the metal), allowing for the gate to control charge flow from the drain to the source without any loss of current (aside from those used in parasitics)

Netlist

A machine-readable file that contains all of the connections in your design. While RTL is human-readable, it is very difficult for a simulator to directly interpret. Instead, we often synthesize our RTL into a gate-level netlist, which specifies all of the gates used in our design, as well as their connections, allowing a machine to understand and simulate the design. This is usually the first step in any ASIC flow.

Network Topology

The physical/logical arrangement of nodes and connections in a network. In hardware, this usually refers to the arrangements of blocks, transistors, etc in a chip connected by wires.

A specific manufacturing process and its design constraints, also referred to as a given technology. It is a specific PDK that is used to manufacture designs.

Nodes are often associated with a given length (or number, in units of nm). For example, you might refer to the Skywater 130nm node. This number used to refer to the gate's half-pitch and it's length. However, more advanced nodes have strayed away from this meaning, somewhat due to marketing purposes (as well as differences in scaling between the length and the pitch), such that the associated length has lost much/all of its meaning.

A board with electrical contacts and connections, used to assemble a complete circuit on. They are composed of the following materials (going by layer from outside in):

• Silkscreen: A layer of ink used to provide indications on the board. This often includes part indicators (what part should go where), part outlines, and possibly some limited functional description (ex. which way a switch is turned to be on)
• Solder Mask: A thin layer of polymer used to protect the copper we don't want exposed from oxidation, as well as to protect against unwanted solder bridges between neighboring connections. On most circuit boards, this polymer appears as a distinct green
• Copper: Copper traces and planes connect the different components on our circuit board (copper is used for its low resistance)
• Substrate: A glass epoxy (or similar material) is used as a substrate for the board, to provide structural support and insulation for the copper connections

PCB's usually have multiple layers of copper within the substrate to facilitate more complicated circuits with more connections. The minimum is often 2 for top and bottom; 2 and 4 are common, although more custom PCB's may have many

The system that delivers power across your design. This starts from a regulator (either off-chip or on-chip as a Voltage Regulator Module, or VRM), and ends with all of the components on the IC that require power. The goal of the PDN is two-fold:

• Everything that needs power should get it. Because of this, a chip will often include power "rails"; large strips of metal that stretch across the area of the die, connecting down to any component that needs power. This often connects to a power ring; metal rings around the main die area that are associated with given voltages. These connect to the pads associated with those voltages
• The power supply should be stable. Large fluctuations in the voltage of our power supply could affect functionality in our chip. Because of this, decoupling capacitors are often used to "smooth" a power supply; capacitors resist changes in voltage, so they are used to ensure that our voltage doesn't change too much all at once.

The process by which a design is transferred onto a chip. The general outline of steps is:

• Clean the Wafer: Ensure the wafer is clean, such as by using CMP
• Deposit: If the wafer is being etched, a thin film of whatever is being etched is first deposited on the surface. This can be done in a variety of methods, such as Evaporation, Molecular Beam Epitaxy, or Sputtering
• Spin Resist: Photoresist is applied to the wafer, and "spun" to have a smooth, thin layer across the wafer.
• Baking: The resist is often "baked" (heated) to improve adhesion and establish photosensitive properties. It can sometimes even be baked two times (a "soft" bake, followed by a "hard" bake). Additionally, the thickness of the resist can also decrease here by about 25%
• Expose: The wafer is exposed to light (usually UV - smaller wavelengths for greater resolution) normal to the surface through the mask with our desired pattern. This results in the resist being more or less soluble where exposed due to the breaking or forming of polymer bonds (respectively), depending on the type of resist
• Development: Here, the soluble photoresist is chemically stripped away. This leaves behind only the less soluble resist, importantly in our desired pattern
• Etch/Deposit: At this point, we have a layer of photoresist in our pattern on our wafer. At this point, one of two things is done:
  • If we've deposited a material previously, we can etch it using an etchant that doesn't affect our photoresist. The resist will therefore protect the areas that it covers, resulting in us etching the desired pattern into our previous material. This technique is known as etch-back
  • We can also deposit a material, knowing that whatever is deposited on our resist will be removed with the resist, resulting in a layer on the wafer in our pattern. This technique is known as lift-off. Often, the biggest challenge can be to ensure a clean break in the material deposited on the resist versus that deposited on the wafer; to ensure a clean break, we can either use a solvent to swell the resist, or have our process specifically designed to undercut these edges to avoid connection
• Strip Resist: Finally, our remaining resist is stripped away, leaving behind a patterned layer of material

This process is repeated for each layer on the chip to gradually form the entire IC

Three key parameters that affect how our chip will function: process (variations in manufacturing), voltage (at what voltage we operate at), and temperature (at what temperature we operate at). Variations in these three characteristics can affect our design and its timing; because of this, it is important to simulate and verify our design across a range of these parameters to ensure that we meet timing (see Corner)

Process: Variations in our process design that can affect how signals propagate. These refer to the speed of the nMOS and pMOS in our design; specifically:

• FF: Fast nMOS, fast pMOS
• SS: Slow nMOS, slow pMOS
• FS: Fast nMOS, slow pMOS
• SF: Slow nMOS, fast pMOS
• TT: Typical speeds for both nMOS and pMOS

The most important of these are the first two: FF will be the worst case for hold time violations, and SS will be the worst case for setup time violations.

Voltage: Chips can also usually be run and tested at different voltages. Higher supply voltage will increase the speed of signals (at the cost of more power, in accordance with Ohm's Law) due to quicker switching of the transistors. However, with large voltages, this benefit will plateau as the interconnect delay (signal delay from the wires and interconnects) begins to dominate.

Temperature: Typically, chips are tested from a temperature range from -40°C to 125°C. This can have different effects on the propagation speed of a signal. At higher voltages, temperature has a negative effect; speed decreases with temperature. However, at lower voltages, temperature has a positive effect; speed increases with temperature. Because of this, it is important to test our designs across the temperature spectrum for setup and hold time violations

A type of memory where different pieces of data can be accessed "at random" by their address (as opposed to other ways of addressing memory, such as with Serial-Addressed Memory or Content Addressable Memory (CAM)). Specifically, RAM refers to volatile memory, as opposed to nonvolatile memory like ROM.

*Both RAM and ROM fall under the general category of random-access memory, but RAM only refers to volatile memory, leading to confusion over the name. Similarly, ROM refers to non-volatile memory, meaning that it can be written as well as read, making it a misnomer as well.

A light-sensitive material (think syrup-consistency) that is used in photolithography. It is typically composed of resin (a binder that provides physical characteristics, such as adhesion and chemical resistance), sensitizer (a photoactive compound with polymers), and solvent (to keep the resist liquid). Resist comes in two types:

• Positive photoresist becomes more soluble when exposed to light. In photolithography, this means that the developer will wash away the exposed area
• Negative photoresist becomes less soluble when exposed to light. In photolithography, this means that the developer will wash away the non-exposed area

A type of memory where different pieces of data can be accessed "at random" by their address (as opposed to other ways of addressing memory, such as with Serial-Addressed Memory or Content Addressable Memory (CAM)). Specifically, ROM refers to nonvolatile memory, as opposed to volatile memory like RAM.

*See footnote of RAM

A level of representation of hardware. It abstracts away a piece of (synchronous) hardware to how data flows between registers, and the logical operations that are performed on it along the way.

Note that many people will say "At the RTL level", instead of simply "At the RTL", meaning that they say "level" twice, similar to chai tea, naan bread, the Sahara Desert, and an ATM Machine. If you want to be both understood and technically correct, I recommend simply "At the register-transfer level"

The gate of a MOSFET that is "self-aligned" by the MOS capacitor.

Previously, as a chip was built from the ground-up, the source and drain regions of a MOSFET were doped before the gate was placed on top. The gate must therefore be carefully aligned between the doped regions; if the mask was slightly off, the gate would be shifted and cause alignment problems, as it wouldn't cover the whole channel.

With modern processes, gates are "self-aligned"; the MOS capacitor over the gate is formed before the doping of the source and drain regions. In this way, the MOS capacitor can act as a mask for the gate region, such that we can dope all around the MOS capacitor, and have the channel region protected by the MOS capacitor, ensuring that our source and drain doped regions go right up to the channel. In this way, the gate aligns itself, hence "self-aligned"

A timing constraint present in synchronous circuits. Specifically, setup time is the amount of time that an input signal (to a register) must remain constant before a clock's positive edge. If the clock edge causes this input to change within our hold margin (the amount of time before an edge with a duration of our setup time), the output and stored state may be unpredictable; in this case, we have violated setup time.

Compared to hold time violations, this is an easier issue to fix; in the worst case, we just slow down our clock speed, so that while our hardware may run slower, all signals would have time to propagate as far as they need to.

A representation of how something would behave; in our case, how computer hardware would proceed. Simulations can come in a variety of flavors (2-State RTL, 4-State RTL, Gate-Level, Back-Annotated GL), depending on how thorough you wish to be; the list above increases in precision, but also simulation time.

If a simulation takes too long, an FPGA can often be used to emulate the desired hardware, allowing for faster "simulation" times.

A difference in timing between when clock signals arrive at different points of the design. This is specifically relevant between two registers where the data transmitted by one is received by the other. The type of skew indicates how much time later the receiving register received the clock signal compared to the transmitting register; positive skew indicates time was added to the receiving register's signal, and it arrives later, whereas negative skew indicates time was taken away, and the receiving register gets the clock earlier.

Clock skew can affect our setup and hold time constraints. Our clock tree aims to minimize skew between closely-connected parts of a design.

A concept where all of the different computing modules (such as a CPU, memory, I/O ports, graphics units, etc.) are all integrated onto a single chip. This contrasts with a motherboard approach, where the different units are separate chips connected on the PCB. For the same functionality, SoC's have higher performance and lower power consumption (as they don't need to drive signals across the PCB), as well as less overall die area. However, this comes at the cost of reduced replaceability; if one module isn't working, the whole chip doesn't work, as you can't replace just the one module. 

This becomes apparent when using external IP. Many companies (such as ARM) sell "IP Blocks"; these are modules that can be integrated into your SoC, such as cores, controllers, memory blocks, etc. However, the vendor may need to take extra care to verify them; since they will be integrated on the same die, if the IP turns out to be non-functional, it cannot be easily replaced, and could affect the rest of the chip.

• (noun): A metallic composition, designed to melt under relatively low temperatures (180-190°C, or 360-370°F) and provide electrical and physical connections to components. Solder comes in a spool, and is easily malleable to direct where you want it to go. Historically, it has been made out of tin and lead (you may see "70:30" or "60:40" solder, referring to the fractions of tin and lead, respectively), although lead-free solders have recently been introduced, which require slightly higher temperatures. They may also include a rosin core, to improve adhesion to metal contacts (see Flux)
• (verb): The act of applying solder to establish an electrical and physical connection between contacts.

A mixture of powdered solder, suspended in flux. It can be used similarly to solder for SMD components, but melts easier. To apply it, one usually places solder paste on the pads, puts the component on top, and then directs a heat gun towards the solder paste to reflow it, where the flux melts and causes the solder to adhere to the connections, forming a physical and electrical connection. Solder paste is typically used for smaller connections, as the large amount of flux allows it to "automatically" adhere to the correct locations, assuming the desired contacts are close enough.

Solder paste must be refrigerated when stored in an airtight container, and warmed up to use. It is typically stored in a syringe for manual use. However, for pick-and-place machines, it is stored in a printing mechanism; it is placed where needed, components are placed on top, and then the entire board is heated to reflow all of the solder paste.

A specific type of SOIC package. Specifically, there are three main standards:

• JEDEC MS-012 (3.9mm body width)
• JEDEC MS-013 (37.5mm body width)
• JEITA (formerly EIAJ) Type II (5.3mm body width)

The first two are typically called "SOIC", whereas the third is referred to as "SOP", or even "wide SOIC" (although it is not as wide as the JEDEC MS-013, which may also be referred to as a "wide SOIC")

A network protocol that allows users to remotely access other computers over an unsecured network. Additionally, it may refer to the suite of utilities used to implement said protocol. It began in 1995 as SSH-1, which was later found to have flaws. The current version is SSH-2, which originally used a Diffie-Hellman Key Exchange to establish symmetric cryptography keys, although it also supports other algorithms, such as RSA and EdDSA.

SSH is the method with which we communicate with the C2S2 server. If you are using the keys generated by the setup script, they operate on the RSA algorithm (specifically using a 3072-bit key)

A group of transistors that provide a defined logic function. A standard cell library will include many of these cells (in various views, such as behavioral, physical, etc.) that the tool can use to synthesize the design.

These cells share many common physical characteristics, making them "standard". Included in these are height and power rail location, pitch of inputs/outputs, and transistor sizing (they are usually multiples of one another). This regularity helps the tools to place and route them in an organized, dense fashion.

An informal term for an "internal tapeout" by the design team to signify a significant checkpoint, as well as a design that could be used, should further improvements fail. The term was coined by Professor John Wawrzynek at UC Berkeley around 2010.

The act or process of sending your finalized designs (GDS) to the foundry. The term originated in the 70's, with two prevailing theories as to its origin:

• ASIC files were stored on magnetic tape. Back when companies both designed and manufactured, this meant that the tape was carried out the door to the foundry; hence, "tapeout"
• Early IC's were made with sticky tape to create the masks during fabrication (similar to PCB's)

While Weste and Harris prefer the first explanation, the second is more likely, as early VLSI designers used paper tape before magnetic tape

ICs are often characterized based on their complexity:

That being said, VLSI has become a general term for the process and techniques involved in combining many transistors on a single custom chip.