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A piece of hardware meant to accelerate a specific task. This is useful when you know that you are likely to be performing a specific task over and over again, and wish to have dedicated hardware to perform it. For example, if you are designing a chip to go in a car, you might have an A* algorithm accelerator to speed up the computation of calculating the shortest route to a destination.

Many designs also have accelerators coupled with general-purpose hardware. This allows for general computations, but adding the option to use the accelerator when beneficial.

A piece of hardware that converts an analog signal (with a continuous spectrum of values) to a digital signal (with discrete values). It is one of the projects for the Analog subteam '23-'24

A design principle that includes considerations of how the design might be tested, extending the design to make the testing process easier. This could include extra functionality and/or more exposure of the design (bringing more nets out to pins) to provide the tester with greater capability to test different parts of the chip.

(Note that this can also stand for Discrete Fourier Transform, which isn't as relevant to overall chip design)

A style of dynamic logic. Here, nodes are precharged high. Once indicated by a clock signal, the nodes are then evaluated; if required by the logic, they are pulled low. In doing so, we only need to implement the PDN, resulting in faster overall logic; domino logic is considered to be the fastest overall logic family, and is often used for high-speed arithmetic. However, it does come with some prerequisites:

• The inputs must be monotonically increasing, or else the dynamic node might be intermediately discharged when we want it to remain high. However, the outputs of the domino stage are monotonically decreasing, making them difficult to chain together. This can usually be resolved with intermediate inverters between stages, or with p-logic stages between the n-logic stages (introducing no-race, or NoRa logic)
• The inputs must be low before the evaluate stage, to avoid early discharging. If this cannot be guaranteed, a footer is used to prevent discharge in the precharge phase (which comes at the cost of higher capacitance that the clock must drive, as well as larger nMOS to maintain a balanced gate)

The process of introducing charge carriers into a silicon lattice. Silicon is a Group 4 element, and forms a nice lattice structure, with each Si forming 4 bonds with its neighbors. When we introduce Group 5 or 3 elements, these will abide by the lattice structure to produce 4 bounds, but will additionally contribute either an electron, or a lack of an electron (known as a hole), both of which can carry charge across the silicon. Because of this, doping comes in two types:

• p-type doping: Introducing Group 3 elements to generate holes in the silicon (usually Boron or Gallium). This forms p-type silicon
• n-type doping: Introducing Group 5 elements to generate electrons in the silicon (usually Arsenic or Phosphorus). This forms n-type silicon

A step in the ASIC flow that determines the final placement of cells. This is after global placement has approximately placed all cells; with detailed placement, we're resolving any overlapping cells, as well as ensuring correct abutment contacts (such as for power and ground rails). This ability to limit our scope makes the final placement process easier.

A type of RAM that passively holds the state (dynamically). It is composed of an access transistor and a capacitor. When we want to access the cell (either to read or write), we set the access transistor to allow current flow, and either charge/discharge the capacitor (write) or read the stored value (read). Given that capacitors naturally discharge over time, DRAM cells must be periodically refreshed. However, capacitors can be made to have a small footprint (look up trench capacitors). Because of this, when compared to registers and SRAM, DRAM uses the least area for a given amount of memory (is the most dense). It additionally uses the least power, at the cost of being the slowest to access.

The process of checking whether our design is manufacturable, according to our PDK. This includes checking the dimensions of transistors, whether traces are too close or far, as well as if we have any antenna violations. This does not check whether our design functions as intended - that is done by LVS, leading to the two often being performed together. If a design has no DRC errors, it is said to be DRC clean.

If your design is not DRC clean, not only will it not be manufactured correctly, but it may cause damage to the fabrication machines. Because of this, a foundry will not manufacture any designs that are not DRC clean.

A step in the ASIC flow that determines the final routing of cells. This comes after global routing, which routes all long global wires to their approximate destinations. With detailed routing, we take a local view of any remaining routing, and ensure that our traces connect to all of our cells. This ability to limit our scope makes the final routing process easier.

A testing methodology that isolates a design as the "design under test". Much of the surrounding framework is abstracted to functional-level models, to isolate the exact component we're testing. Specifically, DUT frameworks often include:

• Generator: Generates the inputs for the DUT
• Driver: Delivers the generated inputs to the DUT
• Monitor: Monitors the output ports (and occasionally input as well) to capture the results of the inputs
• Scoreboard: Compares the outputs of the DUT with the expected outputs
• Environment: Contains the Generator, Driver, Monitor, and Scoreboard, for later re-use (possibly across different modules)
• Test: A given Environment with specific configurations. These configurations can later be tweaked for a different Environment configuration

A style of logic or memory where information is stored dynamically; it is held only temporarily. An example is DRAM, where our memory is held by a large capacitor, but is only held temporarily (leading to the need for a periodic refresh of DRAM memory)

A type of power consumption that occurs from the switching of transistors and computation. Current is used to charge the gate of transistors, and is dumped to ground when they are discharged, leading to power consumption. This is the opposite of static power consumption.

A timing constraint present in synchronous circuits. Specifically, hold time is the amount of time that an input signal (to a register) must remain constant after a clock's positive edge. If the clock edge causes this input to change within our hold margin (the amount of time after an edge with a duration of our hold time), the output and stored state may be unpredictable; in this case, we have violated hold time.

Compared to setup time violations, this is far worse issue; hold time violations are near impossible to fix after tapeout. There are some tricks that can be played (such as cooling the chip or running at a lower voltage to increase signal propagation time), but to a large extent, they are "chip killers", and should be treated with diligence.

A separate or embedded language (relative to our normal HDL) that is meant purely for verification, as opposed to the simulation or synthesis that our HDL is meant for. HVL's often include (non-synthesizable) higher-level constructs and functionality to assist the user in testing their design, such as stimuli generators and assertions, many of which are often wrapped in an object-oriented presentation. Examples include OpenVera, PSL, and the SystemVerilog Verification Subset.

(Note: On Project Teams specifically, HVL can also refer to the High Voltage Laboratory, a (now non-functional) off-campus power maintenance building that is used by some teams for storage. If you hear a random person in the ELL reference HVL, they're probably not verifying a hardware design)

Netlist

A machine-readable file that contains all of the connections in your design. While RTL is human-readable, it is very difficult for a simulator to directly interpret. Instead, we often synthesize our RTL into a gate-level netlist, which specifies all of the gates used in our design, as well as their connections, allowing a machine to understand and simulate the design. This is usually the first step in any ASIC flow.

Network Topology

The physical/logical arrangement of nodes and connections in a network. In hardware, this usually refers to the arrangements of blocks, transistors, etc in a chip connected by wires.

A specific manufacturing process and its design constraints, also referred to as a given technology. It is a specific PDK that is used to manufacture designs.

Nodes are often associated with a given length (or number, in units of nm). For example, you might refer to the Skywater 130nm node. This number used to refer to the gate's half-pitch and it's length. However, more advanced nodes have strayed away from this meaning, somewhat due to marketing purposes (as well as differences in scaling between the length and the pitch), such that the associated length has lost much/all of its meaning.

The gate of a MOSFET that is "self-aligned" by the MOS capacitor.

Previously, as a chip was built from the ground-up, the source and drain regions of a MOSFET were doped before the gate was placed on top. The gate must therefore be carefully aligned between the doped regions; if the mask was slightly off, the gate would be shifted and cause alignment problems, as it wouldn't cover the whole channel.

With modern processes, gates are "self-aligned"; the MOS capacitor over the gate is formed before the doping of the source and drain regions. In this way, the MOS capacitor can act as a mask for the gate region, such that we can dope all around the MOS capacitor, and have the channel region protected by the MOS capacitor, ensuring that our source and drain doped regions go right up to the channel. In this way, the gate aligns itself, hence "self-aligned"

A timing constraint present in synchronous circuits. Specifically, setup time is the amount of time that an input signal (to a register) must remain constant before a clock's positive edge. If the clock edge causes this input to change within our hold margin (the amount of time before an edge with a duration of our setup time), the output and stored state may be unpredictable; in this case, we have violated setup time.

Compared to hold time violations, this is an easier issue to fix; in the worst case, we just slow down our clock speed, so that while our hardware may run slower, all signals would have time to propagate as far as they need to.

A representation of how something would behave; in our case, how computer hardware would proceed. Simulations can come in a variety of flavors (2-State RTL, 4-State RTL, Gate-Level, Back-Annotated GL), depending on how thorough you wish to be; the list above increases in precision, but also simulation time.

If a simulation takes too long, an FPGA can often be used to emulate the desired hardware, allowing for faster "simulation" times.

A difference in timing between when clock signals arrive at different points of the design. This is specifically relevant between two registers where the data transmitted by one is received by the other. The type of skew indicates how much time later the receiving register received the clock signal compared to the transmitting register; positive skew indicates time was added to the receiving register's signal, and it arrives later, whereas negative skew indicates time was taken away, and the receiving register gets the clock earlier.

Clock skew can affect our setup and hold time constraints. Our clock tree aims to minimize skew between closely-connected parts of a design.

A concept where all of the different computing modules (such as a CPU, memory, I/O ports, graphics units, etc.) are all integrated onto a single chip. This contrasts with a motherboard approach, where the different units are separate chips connected on the PCB. For the same functionality, SoC's have higher performance and lower power consumption (as they don't need to drive signals across the PCB), as well as less overall die area. However, this comes at the cost of reduced replaceability; if one module isn't working, the whole chip doesn't work, as you can't replace just the one module. 

This becomes apparent when using external IP. Many companies (such as ARM) sell "IP Blocks"; these are modules that can be integrated into your SoC, such as cores, controllers, memory blocks, etc. However, the vendor may need to take extra care to verify them; since they will be integrated on the same die, if the IP turns out to be non-functional, it cannot be easily replaced, and could affect the rest of the chip.

• (noun): A metallic composition, designed to melt under relatively low temperatures (180-190°C, or 360-370°F) and provide electrical and physical connections to components. Solder comes in a spool, and is easily malleable to direct where you want it to go. Historically, it has been made out of tin and lead (you may see "70:30" or "60:40" solder, referring to the fractions of tin and lead, respectively), although lead-free solders have recently been introduced, which require slightly higher temperatures. They may also include a rosin core, to improve adhesion to metal contacts (see Flux)
• (verb): The act of applying solder to establish an electrical and physical connection between contacts.

A mixture of powdered solder, suspended in flux. It can be used similarly to solder for SMD components, but melts easier. To apply it, one usually places solder paste on the pads, puts the component on top, and then directs a heat gun towards the solder paste to reflow it, where the flux melts and causes the solder to adhere to the connections, forming a physical and electrical connection. Solder paste is typically used for smaller connections, as the large amount of flux allows it to "automatically" adhere to the correct locations, assuming the desired contacts are close enough.

Solder paste must be refrigerated when stored in an airtight container, and warmed up to use. It is typically stored in a syringe for manual use. However, for pick-and-place machines, it is stored in a printing mechanism; it is placed where needed, components are placed on top, and then the entire board is heated to reflow all of the solder paste.

A specific type of SOIC package. Specifically, there are three main standards:

• JEDEC MS-012 (3.9mm body width)
• JEDEC MS-013 (37.5mm body width)
• JEITA (formerly EIAJ) Type II (5.3mm body width)

The first two are typically called "SOIC", whereas the third is referred to as "SOP", or even "wide SOIC" (although it is not as wide as the JEDEC MS-013, which may also be referred to as a "wide SOIC")

A network protocol that allows users to remotely access other computers over an unsecured network. Additionally, it may refer to the suite of utilities used to implement said protocol. It began in 1995 as SSH-1, which was later found to have flaws. The current version is SSH-2, which originally used a Diffie-Hellman Key Exchange to establish symmetric cryptography keys, although it also supports other algorithms, such as RSA and EdDSA.

SSH is the method with which we communicate with the C2S2 server. If you are using the keys generated by the setup script, they operate on the RSA algorithm (specifically using a 3072-bit key)

A group of transistors that provide a defined logic function. A standard cell library will include many of these cells (in various views, such as behavioral, physical, etc.) that the tool can use to synthesize the design.

These cells share many common physical characteristics, making them "standard". Included in these are height and power rail location, pitch of inputs/outputs, and transistor sizing (they are usually multiples of one another). This regularity helps the tools to place and route them in an organized, dense fashion.