Overview
Learn and document how to interface our system with the wishbone bus. This will allow our design to communicate with the CPU!
https://cdn.opencores.org/downloads/wbspec_b4.pdf
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Background
System Requirements
What are the requirements for your system? What functionality must it have? Are there any design space/size requirements? Use the table down below to efficiently document these:
| Requirement Designator | Requirement Explanation |
|---|---|
Interface
The wishbone bus is a hardware computer bus that allows different components to communicate with each other. In the Caravel architecture, the wishbone bus allows the user space to communicate with the RISCV processor. White boxes indicate inputs, blue boxes indicate outputs.
Clock: wb_clk_i | Clock signal, same as the processor clock (10 MHz, 40 MHz maximum) |
Reset: wb_rst_i | Reset signal |
Strobe: wbs_stb_i | Indicates a valid data transfer cycle. Can be thought of as a valid signal for all other signals on the interface. Remains high until ack is asserted |
Cycle: wbs_cyc_i | Indicates a valid bus cycle is in process |
Writeenable: wbs_we_i | Indicates a read or write transaction. Low for reads, high for writes |
Select: wbs_sel_i | Indicates where valid data is expected on data lines. Bitwidth 4 -> each select signal corresponds to each of 4 active bytes on 32 bit data line |
Datain: wbs_dat_i | Input data |
Address: wbs_adr_i | Input data address. Addresses for wishbone responder modules lie in the range 0x 3000_0000 up to 0x3fff_ffff |
Acknowledge: wbs_ack_o | Indicates normal termination for a bus cycle |
Dataout: wbs_dat_o | Output data |
The official specification for the wishbone bus is here:
| View file | ||||
|---|---|---|---|---|
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Implementation
Timeline
Include a timeline of tasks and/or milestones for your project (with dates). This should be decided at the beginning, and reviewed throughout the semester to evaluate whether the project is on schedule or not. This can take the form of either a Gantt chart or a Confluence task list (click the "+" button, and select "Task List")
Files
Give a brief overview of the file structure involved in your design, including where they are stored (ex. link to GitHub repo), as well as maybe a one-sentence description for each
Theory of Design
How did you come up with your design? What is the overall structure or design methodologies involved? This is where one might include block diagrams, FSM diagrams, or anything along those lines relevant to the design, as well as (brief) explanations for any non-obvious algorithms
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Testing
Testing Strategy
What was your overall testing strategy? What types of testing did you perform?
Running Tests
Include step-by-step instructions on how to run the tests on your design (from a clean clone, if stored on GitHub)
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Appendix
Resources
Include links to any resources that you used for your design, including other projects, algorithms, etc. The idea is that others who are interested in your project can explore these as well, and that they might provide helpful background knowledge
https://caravel-harness.readthedocs.io/en/latest/index.html
Lessons Learned
To be filled out as you go! What are some of the lessons you learned while completing your project? They can be technical or soft skills (such as time management, collaboration, etc.)