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| Acronym/Jargon | Means | Definition |
|---|---|---|
| Harden | The process of converting a design from RTL to a final GDS. This is where a design converts to represent the final layout of the chip. "Harden" indicates that this final layout is much more difficult to manipulate than our RTL, as well as that it is the final design. | |
| HDL | Hardware Description Language | A coding language that is meant to represent and model hardware, as opposed to representing a program or other software entity. The two most common are Verilog/SystemVerilog and VHDL, although others do exist, including Amaranth, Bluespec, Chisel, and PyMTL. |
| HLS | High-Level Synthesis | The process of synthesizing a design from a high-level HDL. These languages generally sacrifice precise control over the exact hardware for productivity in representing the overall algorithm, allowing users to iterate across and explore the design space much more efficiently. HLS tools usually have their own flow for bringing their representation down to a lower-level representation, such as Verilog, VHDL, or a gate-level model. |
| Hierarchy | A design methodology that requires splitting large, complicated designs into modular components. These modular components can also be split into a lower level of components, and so on, until design complexity becomes manageable. This not only gives us the benefits of modularity, but enables us to have a manageable level of design complexity at each stage. These levels can also be referred to as hierarchy. | |
| Hold Time | A timing constraint present in synchronous circuits. Specifically, hold time is the amount of time that an input signal (to a register) must remain constant after a clock's positive edge. If the clock edge causes this input to change within our hold margin (the amount of time after an edge with a duration of our hold time), the output and stored state may be unpredictable; in this case, we have violated hold time. Compared to setup time violations, this is far worse issue; hold time violations are near impossible to fix after tapeout. There are some tricks that can be played (such as cooling the chip or running at a lower voltage to increase signal propagation time), but to a large extent, they are "chip killers", and should be treated with diligence. | |
| HVL | Hardware Verification Language | A separate or embedded language (relative to our normal HDL) that is meant purely for verification, as opposed to the simulation or synthesis that our HDL is meant for. HVL's often include (non-synthesizable) higher-level constructs and functionality to assist the user in testing their design, such as stimuli generators and assertions, many of which are often wrapped in an object-oriented presentation. Examples include OpenVera, PSL, and the SystemVerilog Verification Subset. (Note: On Project Teams specifically, HVL can also refer to the High Voltage Laboratory, a (now non-functional) off-campus power maintenance building that is used by some teams for storage. If you hear a random person in the ELL reference HVL, they're probably not verifying a hardware design |
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