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| Requirement Designator | Requirement Explanation |
|---|---|
Interface
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White boxes indicate inputs, blue boxes indicate outputs.
Clock: wb_clk_i | Clock signal, same as the processor clock (10 MHz, 40 MHz maximum) |
Reset: wb_rst_i | Reset signal |
Strobe: wbs_stb_i | Indicates a valid data transfer cycle. Can be thought of as a valid signal for all other signals on the interface. Remains high until ack is asserted |
Cycle: wbs_cyc_i | Indicates a valid bus cycle is in process |
Writeenable: wbs_we_i | Indicates a read or write transaction. Low for reads, high for writes |
Select: wbs_sel_i | Indicates where valid data is expected on data lines. Bitwidth 4 -> each select signal corresponds to each of 4 active bytes on 32 bit data line |
Datain: wbs_dat_i | Input data |
Address: wbs_adr_i | Input data address. Addresses for wishbone responder modules lie in the range 0x 3000_0000 up to 0x3fff_ffff |
Acknowledge: wbs_ack_o | Indicates normal termination for a bus cycle |
Dataout: wbs_dat_o | Output data |
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Implementation
Timeline
Include a timeline of tasks and/or milestones for your project (with dates). This should be decided at the beginning, and reviewed throughout the semester to evaluate whether the project is on schedule or not. This can take the form of either a Gantt chart or a Confluence task list (click the "+" button, and select "Task List")
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