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| Acronym/Jargon | Means | Definition |
|---|---|---|
| Abstraction | The process of purposefully neglecting finer details of a design (abstracting them away). This is a key concept for chip designers, as we are often working with very large designs. Trying to consider every little detail of a design would quickly become impossible due to the complexity (ex. trying to consider the exact implementation of an OR gate in a large processor). Instead, we often abstract away certain details, depending on where we're working. For example, if I'm working with an SRAM, I might only consider the interface (which address I'm reading from, and the read/write data) as a functional-level model, instead of trying to simulate every SRAM block. This can help reduce the complexity, making it much easier for us to work with designs, as well as for our tools to simulate/manage them. | |
| Abutment | A quality of electrical connections on IC's. Specifically, two nets are connected "by abutment" if there connection occurs simply from touching each other when being placed on the cell, and require no further routing. Think of your computer charger; there's no routing that goes into it, but it's connected to your computer simply by being pressed up against it. | |
| Accelerator | A piece of hardware meant to accelerate a specific task. This is useful when you know that you are likely to be performing a specific task over and over again, and wish to have dedicated hardware to perform it. For example, if you are designing a chip to go in a car, you might have an A* algorithm accelerator to speed up the computation of calculating the shortest route to a destination. Many designs also have accelerators coupled with general-purpose hardware. This allows for general computations, but adding the option to use the accelerator when beneficial. | |
| ADC | Analog-Digital Converter | A piece of hardware that converts an analog signal (with a continuous spectrum of values) to a digital signals signal (with discrete values). It is one of the projects for the Analog subteam '23-'24 |
| Antenna Violation | An antenna violation is when you have a large trace of metal on your chip (which we call the antenna). During fabrication, this can result in a large buildup of charge on the wire, leading to damage to any gates they're connected to (see Section 3.6.1 of CMOS VLSI Design). This is usually solved with jumper or diode insertion. | |
| Architecture | The overall high-level design of a system, indicating how it will complete its tasks. For example, most processors are examples of von Neumann architecture | |
| ARM | Advanced RISC Machines | A family of RISC ISAs (or the company that licenses them, originally known as Acorn Computers, with their first major success being their revolutionary BBC Micro as a personal computer). It is the most widely used family of ISAs at time of writing, with use being dominant in mobile devices, as well as in Apple Silicon machines. |
| ASIC | Application-Specific Integrated Circuit | A custom IC targeted towards a specific purpose (different from a more general-purpose component). It will aim to perform a specific workload better than a general-purpose alternative, either in terms or area, energy, power, and/or cost. |
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| Acronym/Jargon | Means | Definition |
|---|---|---|
| DAC | Digital-Analog Converter | A piece of hardware that converts a digital signals signal (with discrete values) to an analog signal (with a continuous spectrum of values). |
| DEF | Design Exchange Format | A file that includes the information about the physical layout of an IC. However, it does not include information about the connections to the cell; that is included in the LEF file, with both required for a complete view of a cell. They are denoted by the .def file suffix |
| Desoldering Pump | See Solder Sucker | |
| DFT | Design For Test | A design principle that includes considerations of how the design might be tested, extending the design to make the testing process easier. This could include extra functionality and/or more exposure of the design (bringing more nets out to pins) to provide the tester with greater capability to test different parts of the chip. (Note that this can also stand for Discrete Fourier Transform, which isn't as relevant to overall chip design) |
| DIBL | Drain-Induced Barrier Lowering | A phenomenon that occurs in MOSFET's with large VDS. This large voltage lowers the source diode barrier, causing a lower threshold voltage (Vth) and larger drain current (ID) with fewer charge carriers in the channel to overcome. Similar to CLM, this comes at the cost of smaller output resistance/small-signal gain, and with large leakage in cutoff. |
| Die | The patterned piece of silicon that composes our chip. Once a wafer is patterned, it is cut (diced) into individual dies, which are then packaged to form the entire IC. While silicon is typically used today due to its crystalline structure and abundance in nature, research has looked into other Group 4 elements, such as Germanium. | |
| Diffusion | The portion of the MOSFET where charge carriers migrate during operation. This includes the source, drain, and channel. Often times, when two nets are connected through doped silicon, we say that they are connected through diffusion. | |
| Diode Insertion | The process of inserting diodes connected to long traces to resolve antenna violations. In normal operation, these diodes will be reverse-biased, acting as an open circuit and not affecting our trace. However, during manufacturing, the breakdown of these diodes will dissipate any buildup of charge that might harm our transistors. These have the upside that they don't affect any of our routing, but the downside that they take up space on our die, and must be thought of in floorplanning. | |
| DIP | Dual-In-Line Package | A THT IC package where pins are arranged in two rows on either side of the chip. This allows for through-hole connections, as well as ease of connectivity on a breadboard (straddling the center divide). An example of this is the popular 74LS series of logic gates. |
| Domino (Logic) | A style of dynamic logic. Here, nodes are precharged high. Once indicated by a clock signal, the nodes are then evaluated; if required by the logic, they are pulled low. In doing so, we only need to implement the PDN, resulting in faster overall logic; domino logic is considered to be the fastest overall logic family, and is often used for high-speed arithmetic. However, it does come with some prerequisites:
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| Doping | The process of introducing charge carriers into a silicon lattice. Silicon is a Group 4 element, and forms a nice lattice structure, with each Si forming 4 bonds with its neighbors. When we introduce Group 5 or 3 elements, these will abide by the lattice structure to produce 4 bounds, but will additionally contribute either an electron, or a lack of an electron (known as a hole), both of which can carry charge across the silicon. Because of this, doping comes in two types:
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| DPL | Detailed Placement | A step in the ASIC flow that determines the final placement of cells. This is after global placement has approximately placed all cells; with detailed placement, we're resolving any overlapping cells, as well as ensuring correct abutment contacts (such as for power and ground rails). This ability to limit our scope makes the final placement process easier. |
| DRAM | Dynamic RAM | A type of RAM that passively holds the state (dynamically). It is composed of an access transistor and a capacitor. When we want to access the cell (either to read or write), we set the access transistor to allow current flow, and either charge/discharge the capacitor (write) or read the stored value (read). Given that capacitors naturally discharge over time, DRAM cells must be periodically refreshed. However, capacitors can be made to have a small footprint (look up trench capacitors). Because of this, when compared to registers and SRAM, DRAM uses the least area for a given amount of memory (is the most dense). It additionally uses the least power, at the cost of being the slowest to access. |
| DRC | Design Rule Check | The process of checking whether our design is manufacturable, according to our PDK. This includes checking the dimensions of transistors, whether traces are too close or far, as well as if we have any antenna violations. This does not check whether our design functions as intended - that is done by LVS, leading to the two often being performed together. If a design has no DRC errors, it is said to be DRC clean. If your design is not DRC clean, not only will it not be manufactured correctly, but it may cause damage to the fabrication machines. Because of this, a foundry will not manufacture any designs that are not DRC clean. |
| DRT | Detailed Routing | A step in the ASIC flow that determines the final routing of cells. This comes after global routing, which routes all long global wires to their approximate destinations. With detailed routing, we take a local view of any remaining routing, and ensure that our traces connect to all of our cells. This ability to limit our scope makes the final routing process easier. |
| DUT | Design Under Test | A testing methodology that isolates a design as the "design under test". Much of the surrounding framework is abstracted to functional-level models, to isolate the exact component we're testing. Specifically, DUT frameworks often include:
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| Dynamic (Logic/Memory) | A style of logic or memory where information is stored dynamically; it is held only temporarily. An example is DRAM, where our memory is held by a large capacitor, but is only held temporarily (leading to the need for a periodic refresh of DRAM memory) | |
| Dynamic (Power Consumption) | A type of power consumption that occurs from the switching of transistors and computation. Current is used to charge the gate of transistors, and is dumped to ground when they are discharged, leading to power consumption. This is the opposite of static power consumption. |
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