...
| Acronym/Jargon | Means | Definition |
|---|---|---|
| CAD | Computer-Assisted Design | A computer program that assists you in design. While many think of CAD as mechanical, we still refer to our development tools as CAD tools (although another name given is ECAD (Electronic CAD), which usually refers to tools involved in PCB design) |
| Chiplet | A small IC with well-defined functionality, meant to be combined with other chiplets on an interposer (substrate for connecting them). This structure allows for chiplet re-use across systems without needing design files (protecting IP), as well as the ability to test chiplets individually and only use the functional ones, rather than relying on an entire IC combining the functionality being defect-free, improving yield. | |
| CI | Continuous Integration | A workflow that checks whether a design is valid. The idea is that this is done automatically (through some mechanism like GitHub Actions or Jenkins) such that design verification can be improved. This is often also combined with Continuous Deployment (CD), referred to as CI/CD, so that once a design is automatically verified, it can also automatically be build and deployed for use. |
| CISC | Complex Instruction Set Computer | A family of ISAs pioneered by Intel in the late 1970's with x86. Specifically, CISC ISA's define complex instructions that often perform multiple tasks. This leads to easier software development with fewer instructions required. However, it can also lead to more complicated hardware, as decoding and pipelining CISC instructions can be difficult. Because of this, CISC processors often operate at slower clock frequencies than RISC processors. |
| CLM | Channel Length Modulation | A phenomenon that occurs in MOSFET's with large VDS. This large voltage expands the drain's depletion region, shortening the effective length (Leff) of the channel. This improves the ON current of the transistor, but decreases the output resistance/small-signal gain, as well as creating a large amount of leakage when Leff → 0 |
| Clock | An important signal in sequential designs that controls when data transfer occurs. The most common use of clocks is in registers, which store value to their internal state on the rising edge of the clock (when it transitions from 0 to 1) | |
| CMOS | Complementary MOS | A logic style that implements a pull-up network (see PUN) and a pull-down network (see PDN) for digital logic gates. This leads to a very robust logic design (not susceptible to noise, signal is at full voltage level) at the cost of implementing the logic twice in the PUN and PDN, with a slower speed as well |
| CMP | Chemical Mechanical Planarization (or Polishing) | A process to planarize the surface of a die (make it really flat/smooth) during fabrication. A nanocrystal slurry and etchant work together to remove any large structures on the top surface. This is useful because it provides a guaranteed flat surface to build further layers on top of. However, CMP can also cause dishing and erosion when there are large areas of a constant material. To avoid this, tools often insert extra structures not for any electrically functional reason, but to provide a good CMP finish (see Fill) (although sometimes, decoupling capacitors are used to additionally smooth any voltage supply lines). |
| Combinational (Logic) | Logic that doesn't retain any state; the outputs are purely a function of the inputs. | |
| Corner | (Also known as a process corner) A representation of variation in manufacturing that may arise. This simplest representation of these attempt to capture the speeds of our transistors, and are usually represented with two letters to represent the speed of the nMOS and pMOS transistors, respectively:
These are called "corners" as they would be the extremes on an n vs. p mobility graphs. variations in our design/s performance environment that may arise (variations across PVT). It is important to test designs across corners to ensure that it will function correctly under our tolerances for manufacturing . The most important are the last three: TT is what how we'd expect our logic to perform as a baseline, and mismatched nMOS/pMOS speeds could affect our logic. More advanced corners may attempt to cover other parameters, such as voltage and temperature (see PVT)- we make the assumption that if our design functions at the extremes, it will function in between. | |
| Critical Path | The slowest combinational path between sequential elements in a design (the one with the most negative slack). This is the longest path that signals have to take in a clock cycle, and is therefore the path that limits how fast our clock can run. If we want to to use a faster clock, we must optimize/shorten the critical path. | |
| Cross-Talk | A phenomenon that occurs between two large traces that run close to each other. There will be parasitic capacitive coupling between them, meaning that changes in voltage on one trace (known as the aggressor) can cause changes in voltage on the other (known as the victim). Some ways to reduce this are:
Finally, since the parasitic capacitance comes from the overlapping trace area, a good practice is to have neighboring metal layers have perpendicular traces. For example, if the traces on Metal5 run vertically, we'd have the traces on Metal6 run horizontally, to avoid large areas of trace overlap. | |
| CTS | Clock Tree Synthesis | A specific step in our ASIC flow where we form the clock tree. Since our clock is such an important signal, as well as because it has a high fanout, a normal driver would result in a very slow and not-sharp signal. Instead, we form a tree of buffers for our clock signal, such that each buffer drives multiple buffers. This tree allows us to propagate our clock with sufficient drive strength and speed to all the sequential circuits where it's needed. |
| Cycle | A complete repetition of a signal; in digital design, this almost always refers to our clock. A cycle can be measured as the time from one rising edge to the next. Performance of digital circuits is often measured in the number of cycles it takes to complete, indicating how many instances of data transfer need to occur in our sequential circuits to achieve the desired operation. | |
| Cycle Time | The time (usually in nanoseconds) of one cycle of our clock. Shorter cycle time means a faster design. Our cycle time is constrained by our setup time. |
...
| Acronym/Jargon | Means | Definition | |||
|---|---|---|---|---|---|
| Package | The case surrounding a chip, intended to prevent damage/corrosion while allowing external access to the electrical interconnects. Many different styles of packages exist; some are detailed on this page | ||||
| Packet | A collection of data, as well as some other headers (extra metadata), such as the format of the data, its intended destination, and other information that's required to correctly interpret it. The concept of packets is used in networking/interconnects to indicate a chunk of information that is transmitted together. | ||||
| Pad | A large block of metal on a die, intended for external connections. These often (although not always) have some minimal ESD protection associated with them via diodes, as well as large drivers to drive signals off-chip (if they are an output). It is here that we make external connections to the die. Due to the prevalence of wire-bonding, you will most often find pads along the perimeter of the die (see Padring) | ||||
| Padring | The ring of pads that surround a design on the chip. These are located along the perimeter for use in wire-bonding processes. A high-level layout will often include the location of signals among the pads on the padring. Note that Caravel from eFabless comes with its own padring that the user isn't responsible for. | ||||
| Parasitics | Any electrical element that occurs not by design, but as a by-product of layout. For instance, if two nets are close together, there may be some parasitic resistance through whatever's separating them (i.e. they aren't perfectly electrically isolated), even though we didn't intentionally put a resistor there. At some level, parasitic resistance/capacitance/inductance will always exist, but are usually very small; we decide as designers how much we care about them. These parasitics can affect the delay between nodes, the frequencies at which we can operate, and how adjacent nodes or interconnects can affect each other. | ||||
| PCB | Printed Circuit Board | A board with electrical contacts and connections, used to assemble a complete circuit on. They are composed of the following materials (going by layer from outside in):
PCB's usually have multiple layers of copper within the substrate to facilitate more complicated circuits with more connections. The minimum is often 2 for top and bottom; 2 and 4 are common, although more custom PCB's may have many | |||
| PDK | Process Design Kit | A collection of specifications for a factory's manufacturing process. This includes design rules (DRC and LVS), various models of components and standard cells (behavioural, timing, SPICE, etc.), verification tools that can assist a designer, and other specifications (such as the number and dimensions of metal layers). In essence, a PDK contains everything a designer would need to know from the foundry in order to make a design that the factory can manufacture successfully. | |||
| PDN | Power Delivery/Distribution Network | The system that delivers power across your design. This starts from a regulator (either off-chip or on-chip as a Voltage Regulator Module, or VRM), and ends with all of the components on the IC that require power. The goal of the PDN is two-fold:
| |||
| PDN | Pull-Down Network | A component of a transistor-level gate design that pulls the output "down" (drives it to a logical 0) when the appropriate logic conditions are met. This is implemented using nMOS transistors, as they pass 0's better than pMOS transistors can. It is the complement to the PUN. | |||
| Perfboard | See Protoboard | ||||
| PEX | Parasitic Extraction | The process of extracting a design specifically to gain more information about the parasitics involved in layout. This is more common in Digital design (in Analog, it would just be extraction), where our layout was generated by a computer; it will have unintentional parasitics. Capturing these parasitics in extraction allows us to simulate our design with them present, allowing us to verify that our design will still function as intended even with the presence of parasitics (see Back-Annotated) | |||
| PGA | Pin Grid Array | A THT IC package that includes a large array of through-hole pins on the underside. Flip-chip mounts often use this style (FCPGA), gaining the additional benefit of having the die closer to any cooling mechanism present. PGA packages are often also characterized by their substrate, such as ceramic (CPGA), organic plastic (OPGA), or regular plastic (PPGA) | |||
| Photolithography | The process by which a design is transferred onto a chip. The general outline of steps is:
This process is repeated for each layer on the chip to gradually form the entire IC | ||||
| Pinout | (Pronounced pin-out) An association between the electrical contacts ("pins") of a module/chip and their associated function. For instance, a pinout might tell you that the top-left corner of a chip is the "ground" pin for that chip. | ||||
| Pipeline(d) | A quality of a computational system where various steps/stages are separated by registers that store intermediate values. This means that a single transaction might take multiple cycles, but since pipelines are often designed to split up the critical path, the clock can run faster, resulting in faster cycles. This means that the overall transaction latency (the time it takes for one transaction to complete from start to finish) might not be impacted. However, since we can have multiple transactions in the pipeline ("in-flight") at a time, our overall throughput (number of transactions per unit time) will increase, resulting in a faster design. | ||||
| Pitch | The minimum center-to-center distance between interconnects on an IC, given by the PDK. The pitch is often a good representation of how small a PDK is, with smaller nodes being more advanced. It also can help us get rough estimates of how large a design will be. The pitch can be expressed in terms of absolute distance or in terms of lambda (see Lambda Rules) | ||||
| PNR | Place and Route | A step (sometimes viewed as two) in the ASIC Flow. Here, we place our standard cells and other components on the chip, and route them together to connect corresponding nets across the chip. Both of these steps are often separated into "global" and "detailed" versions to allow computers to deal with the task at different levels of complexity (see GPL, DPL, GRT, DRT) | |||
| PR Boundary | Place and Route Boundary | A physical boundary around a standard cell or component, contained in the LEF file. This boundary helps the computer know how much space the cell occupies, so that it can place it alongside others without any overlap or unnecessary gaps. It can also help designers form a early, rough estimate about how much space their design will take up; simply the sum of the area contained in the PR boundaries of all the cells used. | |||
| Processor | A computational engine that takes in instructions and operates on data based on said instructions. Processors near-always interface with memory of some sort to store data. | ||||
| Protoboard | A board that is meant for intermediate circuit development. It contains many holes intended for THT components, as well as pads around the holes to allow for ease of creating solder bridges to connect them. It is more permanent than a breadboard (components are connected and fixed in place by solder), but less permanent than a PCB (connections are still exposed and often not as neat as possible, as it was done by hand with no access to multiple layers) | ||||
| PTL | Pass Transistor Logic | A family of logic styles where values are passed through transistors, as opposed to always being driven to rail voltages as in CMOS. This can lead to faster designs and simpler implementations (non-inverting by nature), at the cost of having to worry about signal integrity in the presence of noise, as well as the ability to drive designs with large fanout. | |||
| PUN | Pull-Up Network | A component of a transistor-level gate design that pulls the output "up" (drives it to a logical 1) when the appropriate logic conditions are met. This is implemented using pMOS transistors, as they pass 1's better than nMOS transistors can. It is the complement to the PDN. | |||
| PVT | Process Voltage and Temperature | Three key parameters that affect how our chip will function: process (variations in manufacturing), voltage (at what voltage we operate at), and temperature (at what temperature we operate at). Variations in these three characteristics can . It is the complement to the PDN. | PVT | Process Voltage and Temperature | affect our design and its timing; because of this, it is important to simulate and verify our design across a range of these parameters to ensure that we meet timing (see Corner)
The most important of these are the first two: FF will be the worst case for hold time violations, and SS will be the worst case for setup time violations. Voltage: Chips can also usually be run and tested at different voltages. Higher supply voltage will increase the speed of signals (at the cost of more power, in accordance with Ohm's Law) due to quicker switching of the transistors. However, with large voltages, this benefit will plateau as the interconnect delay (signal delay from the wires and interconnects) begins to dominate. Temperature: Typically, chips are tested from a temperature range from -40°C to 125°C. This can have different effects on the propagation speed of a signal. At higher voltages, temperature has a negative effect; speed decreases with temperature. However, at lower voltages, temperature has a positive effect; speed increases with temperature. Because Three key parameters that affect how our chip will function: process (variations in manufacturing), voltage (at what voltage we operate at), and temperature (at what temperature we operate at). Variations in these three characteristics can affect our design; becauseof this, it is important to simulate and verifytest our design across a range of these parameters (see Corner)designs across the temperature spectrum for setup and hold time violations |
Q:
| Acronym/Jargon | Means | Definition |
|---|---|---|
| QFN | Quad Flat No-Lead | A SMD IC package that includes many electrical contacts around the perimeter for electrical connections, as well as one large contact on the bottom (commonly used for heat dissipation, and often the ground contact of the chip). This package has no "leads" (pins); the entire base of the package (including all the contacts) is flush, and adheres to the PCB as a surface-mount device. Compared to a QFP package, they are typically smaller in size, and have larger/fewer contacts (fewer than 32) |
| QFP | Quad Flat Package | A SMD IC package that includes many pins/leads around the perimeter. It is used when the chip requires many contacts (32 to 100+). Compared to a QFN package, they are typically larger in size, and have more, smaller contacts. |
...
| Acronym/Jargon | Means | Definition |
|---|---|---|
| Tapein (Tape-in) | An informal term for an "internal tapeout" by the design team to signify a significant checkpoint, as well as a design that could be used, should further improvements fail. The term was coined by Professor John Wawrzynek at UC Berkeley around 2010. | |
| Tapeout (Tape-out) | The act or process of sending your finalized designs (GDS) to the foundry. The term originated in the 70's, with two prevailing theories as to its origin:
While Weste and Harris prefer the first explanation, the second is more likely, as early VLSI designers used paper tape before magnetic tape | |
| Threshold (Voltage) | The voltage between the gate and source of a MOSFET (VGS for nMOS, VSG for pMOS) required to "turn on" the transistor (allow charge carriers to flow from the drain to source). Commonly denoted as Vth, increasing it will result in less static power consumption (the MOSFETs will be less turned on simultaneously, resulting in less short-circuit current), but longer delay (as the MOSFET gate voltage needs to increase more to turn on, taking more time to get to the voltage). | |
| THT | Through-Hole Technology | A style of package that includes legs that go through the PCB to the other side. These components are usually easier to solder onto the PCB (you can apply solder from the other side), but can't be as small/dense as SMD components, as well as somewhat limiting the use of the back layer for other routing (as area is taken up on the back layer by the connections) |
| Timing | To "meet timing" in a design is to ensure that there are no setup and/or hold time violations. | |
| TNS | Total Negative Slack | The sum of all negative slack values across all paths in our design. |
| Trace | A electrical connection made of metal, either on a PCB or IC (think of a wire, but entirely solid and inflexible) |
...