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| Acronym/Jargon | Means | Definition |
|---|---|---|
| Fab | See Foundry | |
| Fanout | A given gate's fanout is the amount of output capacitance it is driving relative to its input capacitance. For example, if an AND gate's output was an input to three other AND gates, it would have a fanout of 3. If it were to instead drive 5 inverters, each of which had half the input capacitance of the AND, it would have a fanout of 2.5. | |
| Falling Edge | The transition of a digital signal from a logical 1 to a logical 0. This transition of a clock signal is rarely used to transfer data compared to its rising edge (unless we're doing something silly like DDR - if you're curious, out of scope for here, but look it up | |
| FFT | Fast Fourier Transform | A mathematical operation that takes a time domain signal and converts it into a frequency domain signal. Specifically, a Fast Fourier transform attempts to speed up the computation by eliminating many of the redundant operations originally present in the Fourier algorithm. This was the design present on C2S2's Digital Spring 2023 tapeout! |
| (Metal) Fill | Metal shapes inserted on our chip that serve no logical purpose. Instead, their role is more structural, serving to keep our metal density/distribution even across the layer to avoid variations in thickness after CMP. | |
| Filler Cell | A standard cell that doesn't have a logical function, but is instead used to ensure power connections by abutment. Often times, our standard cells get their power and ground from their neighbors, relying on the fact that power and ground will be in the same location across all standard cells. During placement, we may find that our standard cells are spaced out, meaning that power and ground won't be connected. Our filler cells are just these connections, and are placed in the gaps to ensure that power and ground can go from one neighbor to another. | |
| FinFET | A style of transistor occurring in small process nodes (nominally 22nm or below). They have the area of diffusion sticking up perpendicular to the substrate, instead of laying parallel on top (looking up a picture helps). This allows the gate of the transistor to wrap around this area and cover three sides, giving the gate much more control over the source-drain current (lowering the threshold voltage, saving power...all sorts of good stuff). Future development include "gate all-around"; which this is mostly theoretical at time of writing (Intel claims they'll be able to do it | |
| Flip Chip | A method of connecting the interconnects of a die to other dies and its packaging (specifically, the leadframe). Specifically, flip chip calls for turning the die upside-down, such that the top layer of metal (now on the bottom) can directly contact the packaging to connect. Compared to wire bonding, the primary advantage is the density of interconnects (proportional to area, not just the perimeter), as well as shorter interconnects (leading to faster speeds). However, this comes at the cost of more complicated, less flexible manufacturing, as well as the cost to manufacture. | |
| Floorplan(ing) | The process of (or result of) determining where our design will be placed on our silicon die, and how much area it will take up. Often times, there is non-negligible overhead in routing our design; because of this, our floorplan might not be as compact as it could be. However, it's difficult to know this overhead exactly beforehand, as we have to know where our design is located before routing. Because of this, our floorplan tool will often target a specific density of our design; how close together all of the blocks and standard cells should be. After routing, there may be leftover space because of this. This is often filled with other devices to ensure a quality CMP process; these may be non-functional, but a common choice is decoupling capacitors to ensure a smooth and steady voltage supply. | |
| (ASIC) Flow | An "automated" process to turn an RTL design into a final GDS file. "Automated" is in quotes, as the tools involved usually need a fair amount of help and guidance from the user to generate a good design. While all flows are different, the common steps (in rough order) are:
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| Footprint | A 2-dimensional diagram of the connections of a component to the PCB. To include a component in your PCB design, you need its footprint in order to know the location and size of each connection. | |
| Foundry | The place/company/entity that fabricates the final design (the factory). Previously, this was often lumped in with the designers (leading to vertically integrated chip design). However, more modern trends have seen a separation of fabrication from design, and many design companies going fabless. This allows the designers and foundries to work with many more partners, but additionally poses challenges in maintaining the security of IP. Some examples of foundries are TSMC, Skywater, and Global Foundries. Some examples of fabless designers are Qualcomm, Broadcom, Nvidia, Xilinx, AMD, Marvell, and eFabless. Some examples of integrated companies include Intel and Samsung. | |
| FPGA | Field-Programmable Gate Array | A reconfigurable piece of hardware that can emulate hardware designs. It does this through many programmable lookup tables (LUTs) which are all interconnected, allowing the user to program the FPGA to emulate hardware by defining the output logic of the LUTs and how they are connected. Due to their programmability/flexibility, FPGA's aren't as efficient as ASIC designs. However, they are still much faster than simulations of hardware, with their flexibility causing many consumers to use them (ex. to train your neural network, instead of having to go through the tapeout process with a high startup cost to make an ASIC to do it, companies will rent you out time on their FPGA's, saving you money). In general, FPGA's are preferred for small quantities, whereas ASICs are preferred for large quantities (with the crossover point varying, but currently around 100,000) |
| FSM | Finite State Machine | A design that includes an internal piece of "state" (of which there are predefined options) that represents the current status of the design. When designing an FPGA, we need to consider the three following items:
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