Overview
A delta-sigma ADC is a system that modulates an analog signal into the frequency domain. The output is essentially a bit-string that can be read by digital systems.
Background
System Requirements
Requirement | Value | Requirement Explanation |
---|---|---|
Input frequency range | 20-20kHz | Human audible range |
Input amplitude | ||
Orders of Modulation | 2 | Allows for lower frequency oversampling, while keeping the footprint small |
Effective bit resolution | 8 1/2 | Necessary to discern high-pitched bird noise |
Schematic (WIP)
Second-Order Delta-Sigma Modulator
Implementation
Timeline
- Design plan
- Design and test low-frequency first-order modulator
- Convert to second-order modulator
- Push to design frequency
- Remove idealized components and adjust for sky130
- Begin layout and routing
Files
All of the files involved with this project are stored in a GitHub repository as part of C2S2's organization. The file organization is as follows:
Theory of Design
A Delta-Sigma Modulator (DSM) is a type of analog-to-digital converter (ADC) that converts analog signals into digital signals. It's commonly used in applications where high-resolution conversion is needed, such as in audio and communication systems. The basic idea behind a Delta-Sigma Modulator is to use a one-bit quantizer in a feedback loop, which oversamples the input signal and produces a high-density data stream that can be decimated to obtain the digital output.
- The Delta Sigma ADC is composed of three main parts: the modulator, digital filter, and decimator.
- The modulator is the biggest and most important challenge in designing a delta-sigma ADC.
- A modulator works in a feedback loop with an oversampling clock frequency. This clock signal is subtracted from the input signal, which is then integrated. This signal is then fed into a latched comparator (1-bit ADC), that can inhibit the clock signal in the feedback loop.
- The intended output is a square wave, which, when averaged, can produce the input analog signal.
- The 0-signal corresponds to the clock signal at the output (0 average)
- A large input creates a longer duty cycle and longer period at the output, which averages to a greater value.
Testing
Testing Strategy
<TBD>
Running Tests
<TBD>
Appendix
Resources
- Project GitHub repository
- Existing Caravel testing framework
- Caravel UART documentation
- Caravel User Project Area GPIO Configuration
- Makefile Pattern Rules (for compilation)