C2S2 currently has three primary development environments available:

C2S2's environment is built on top of these operating systems with our toolchain using EasyBuild, with minimal operating system dependencies. Below is a list of all currently maintained packages as part of C2S2's development environment.

In an ideal world, these packages would be reviewed once a year, with many upgrades to current releases (verified against regressions), reflecting an increase in the major version of the toolchain.

Note that additional packages/systems may be available as part of the dependency tree needed to install these packages. Their presence and versions is NOT guaranteed, and should not be relied upon without explicit inclusion in the toolchain. Such packages are not listed here, but can be found in the modules directory at the installation path

v1.0 - Taughannock

PackageDescriptionHomepageCategoryVersionNotable BinariesDev Notes
binutils GNU binary utilitiesHomepage

2.40 ld , ar 
C2S2PythonPackages C2S2's collection of python packagesConfluence Page

2024.02 See Confluence Page
CMake CMake, the cross-platform, open-source build system. CMake is a family of tools designed to build, test and package softwareHomepage

3.27.6 cmake
GCCcore The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Java, and Ada, as well as libraries for these languages (libstdc++, libgcj,...)Homepage

13.2.0 gcc , g++ 
gaw3 Gaw is a Linux software tool for displaying analog waveforms from sampled datas; for example, from the output of simulators or input from sound cardsHomepage

20220315 gaw 
git Git is a free and open source distributed version control system designed to handle everything from small to very large projects with speed and efficiency.Homepage

2.42.0 git 
gtkwave GTKWave is a fully featured GTK+ based wave viewerHomepage

3.3.117 gtkwave 
gzip gzip  (GNU zip) is a popular data compression program as a replacement for compress Homepage

1.13 gzip , gunzip 
iverilog A general-purpose Verilog HDL compilerDocumentation

12.0 iverilog , vvp 
Java Java Platform, Standard Edition (Java SE) lets you develop and deploy Java applications on desktops and serversHomepage

17.0.6 javac , java 
klayout A high-performance layout viewer and editor with support for GDS and OASISHomepage

0.28.17 klayout 
magic Magic is a venerable VLSI layout tool written (and responsible for) TclHomepage

8.3.462 magic 
make GNU Make is a tool which controls the generation of executables and other non-source files of a program from the program's source filesHomepage

4.4.1 make 
netgen A LVS tool for comparing SPICE or Verilog netlistsHomepage

1.5.271 netgen 
ngspice An open source SPICE simulator for electric and electronic circuitsHomepage

42 ngspice 
Perl-bundle-CPAN Many common packages from CPAN for PerlPerl, CPAN, packages

5.38.0 perl (in Perl/ dependency)
Python A high-level, general-purpose programming language with emphasis on readability, quick development, and a well-supported library ecosystem.Homepage

3.11.5 python / python3 , pip 
riscv-gnu-toolchain The RISC-V C and C++ cross-compiler, similar to GCC but with the riscv64-unknown-elf- prefixSource

2024.02 riscv64-unknown-elf-gcc 
Rust A multi-paradigm, general-purpose programming language that emphasizes performance, type safety, memory safety, and concurrency.Homepage

1.73.0 rustc , cargo 
sky130 A collaboration between Google and Skywater Technology Foundry to create an open-source PDKCode, Documentation

2024.04 
Exports PDK_ROOT as the location, as well as PDK=sky130A 
svlint A SystemVerilog linterCrates Page

0.9.2 svlint 
svls A SystemVerilog language serverCrates Page

0.2.11 svls 
tmux An open-source terminal multiplexer allowing for disconnected sessionsHomepage

3.3a tmux 
verilator An open-source Verilog/SystemVerilog simulator focused on speedHomepage

4.036 verilator Significantly outdated, but maintained for the pymtl3 Python package
xclip A command-line interface to the X11 clipboardLinux man page

0.13 xclip 
xschem A schematic capture program; it allows creation of hierarchical representation of circuits with a top down approachHomepage

3.4.4 xschem 
yosys A framework for Verilog RTL synthesisHomepage

0.38 yosys