Below is an image of the work in progress flashADC components and some testing results (for max delay in corners, which is measured from when the clock is at 1/2Vdd to when the digital output is at 1/2Vdd).
The files can be found in the following location: https://github.com/cornell-c2s2/Analog_FA23_SP24/tree/dev/flashADC
Top level schematic:
Class AB Comparator Schematic:
RS Latch Schematic:
This custom RS latch original journal article can be found at this location: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=845191
The RS latch was designed with symmetry in mind, so that Q and !Q transition at the same point. Simulated waveform found here:
Priority Encoder Schematic:
Delay Table for Corners:
| Max Delay by Corner (ns) | ||||
|---|---|---|---|---|
| TT | FF | SS | FS | SF |
| 2.1516 | 1.5726 | 3.1265 | 1.8645 | 2.7132 |
Sample Output and View at Certain Stages (there are glitches at the output, but they stabilize within less than 1/10 of the desired 25MHz clock frequency period):
